Breaking AI computing bottleneck: technical revolution and engineering breakthrough of glass substrate packaging

A silent revolution is taking place in the field of semiconductor packaging. With the proliferation of AI chip transistors, the traditional organic substrate has become exhausted: AMD’s new generation EPYC processor integrates 192 cores, NVIDIA GB200 has repeatedly delayed mass production due to heat dissipation and high power consumption, and the thermal deformation, signal loss and interconnection density bottlenecks of the traditional organic substrate have become the key shackles of the leap in computing power. Intel, Samsung, TSMC and other industry giants have bet on a subversive material—— Glass substrate 。 It is not only the replacement of materials, but also the reconstruction of packaging paradigm.

1、 Performance transition: underlying technology logic of glass substrate

The core value of glass substrate is that its physical characteristics are highly consistent with the strict requirements of semiconductor packaging:

Thermal stability failure : The coefficient of thermal expansion (CTE) of glass is 3-9 ppm/K, which is highly matched with the silicon chip (2.9-4 ppm/K), completely solving the problem of organic substrate warpage in thermal cycle. Taking Intel’s measured data as an example, the deformation of glass substrate package after high-temperature reflow soldering is only 1/5 of that of organic substrate, significantly reducing the risk of stress failure between chip and substrate.
Breakthrough in electrical performance : The dielectric constant (~5) of glass is only 1/3 of that of silicon, and the dielectric loss (tan δ is as low as 1 ‰ – 2 ‰ @ 500MHz) is 2-3 orders of magnitude lower than that of silicon. This means that the signal transmission loss can be reduced by more than 70%. Especially for D-band (110-170 GHz) millimeter wave communication, the glass interlayer can achieve antenna gain with return loss<- 20dB.
3D integration revolution : Made by laser induced etching (LIDE) technology Glass through hole （TGV）， The depth width ratio can reach 20:1, and the spacing can be reduced to 50 μ m. This has increased the interconnection density per unit area by 10 times. Intel has measured that the glass substrate can accommodate 50% more die, providing a physical basis for the heterogeneous integration of Chiplet.

2、 Engineering core: tackling key problems of TGV technology and material system

The core of realizing the landing of glass substrate packaging lies in two technical pillars:

1. TGV process chain: precise control from pore forming to metallization

“Cold working” hole forming technology : Selective laser induced etching (LIDE) uses femtosecond laser to induce the modified area of nano grating in the glass, and then selectively etches with hydrofluoric acid to form a crack free via with smooth side walls (roughness<0.1 μ m). Compared with direct laser ablation, LIDE reduces the risk of microcracks by 90% and increases the yield to 99%.
Metallization scheme of thermal stress coordination ：
- Fully filled copper : The conductivity and heat dissipation are optimal, but the mismatch between copper (CTE=17ppm/K) and glass CTE results in “copper bulge”, and the bulge height can reach 3 μ m at high temperature;
- Conformal copper plating : The hole wall is copper plated (2-5 μ m thick), the center is filled with polymer, and the thermal stress is reduced by 50%, which is suitable for high-density TGV arrays;
- Conductive paste filling : The modulus of copper paste is only 30GPa, and the stress is absorbed by “overcoming hardness with softness”, but the resistivity is 20% higher than that of pure copper.

Table: Engineering trade-offs of TGV metallization strategy

Programme	Resistivity	Thermal conductivity	Thermal stress	Applicable scenarios
Fully filled copper	minimum	highest	highest	High power chip cooling
Conformal copper plating	secondary	secondary	low	High density interconnection intermediary layer
Conductive paste filling	higher	Lower	minimum	MEMS sensor packaging

2. “Performance engineering” of glass materials

Customized glass components for different application scenarios:

Borosilicate glass (SiO ₂ 80%+B ₂ O ≮ 12% – 13%): CTE ≈ 3.3 ppm/K, perfectly matched with silicon, used for CPU/GPU chip packaging;
Alkali free aluminum borosilicate glass : dielectric loss<1 ‰, suitable for 5G millimeter wave antenna integration;
Photosensitive glass : The process flow is shortened by 30% through direct graphical UV exposure.

3、 Application scenario: leap from heat dissipation dilemma to photon integration

Glass substrate packaging has demonstrated disruptive potential in three high-value fields:

High power chip cooling : In the diamond glass heterostructure integration scheme, the glass substrate acts as an intermediary layer, combined with nano Cu/Au recrystallization bonding, to reduce the peak temperature of the chip by 40%, and increase the power density to 50mW/mm2 (such as isolated DC-DC converter);
MEMS reliable packaging : PZB glass composite containing 30% β – lithium permeating feldspar (CTE=3.26 ppm/K), which reduces the parasitic capacitance of inertial sensor by 60% at 375 ℃, and improves the stability of resonant frequency by 2 times;
Photon electron co packaging : D-band elliptical waveguide antenna etches metallized waveguide on glass by laser, and the gain reaches 15.6dB@149GHz The loss is 80% lower than that of organic substrate.

4、 Industrialization process: giant positioning and manufacturing breakthrough

Global semiconductor giants have entered the stage of mass production competition:

Intel : Invest 1 billion dollars to establish a glass substrate R&D line, and mass produce three-layer RDL packages with through-hole spacing of 75 μ m in 2026;
Samsung Alliance : Samsung Display+Samsung Electric will jointly tackle key problems, build a prototype line in 2025, and target mass production in 2026;
Breakthrough in localization : The thick copper technology of Vogel photoelectric glass passed customer verification, and the first domestic TGV board level packaging line was built in Triassic, with the depth width ratio exceeding 10:1, Dinghongrun In the mature process of glass through-hole of (Shenzhen) Technology Co., Ltd., the minimum through-hole diameter has reached 50 nm, and the process technology is still making breakthroughs.

However, the engineering challenges are still severe: the glass brittleness causes the cutting yield to be less than 80%, the TGV metallization equipment needs to be re developed, and the long-term reliability database needs to be accumulated for more than 5 years. The initial cost is expected to be 3 times of the organic substrate, but with the maturity of the panel level packaging (FOPLP) technology, the cost is expected to be reduced to less than 1.5 times in 2030.

The Dispute of Technical Sovereignty in Substrate Reconstruction

Glass substrate packaging is not only a substitute for materials, but also a paradigm transition from “planar interconnection” to “three-dimensional integration”. It solves the underlying contradiction of AI chip in three dimensions of heat dissipation, signal integrity and integration density, and makes Moore’s Law continue to live at the system level. With the completion of the mass production schedule of Intel, Samsung and TSMC, this competition around substrate technology has been upgraded to the strategic control of semiconductor ecology.

In the next five years, the glass substrate will take the lead in the fields of HBM storage stack, GPU chipset and optical module. According to Omdia’s prediction, the global glass substrate market size will exceed 10 billion yuan in 2030, becoming a “new infrastructure” for high-end packaging. The key to truly win this competition is not only the through-hole density or loss index, but also the ability to build a full chain of technical sovereignty from material formula, equipment process to reliability standards.